Modeling and simulation of ZnO-based TFTs by dielectric engineering and temperature analysis for enhanced performance

This work presents the modeling and simulation of thin-film transistors (TFTs) based on zinc oxide (ZnO). Strong agreement was found when the developed device model was validated against experimental data. Additionally, the analog performance of ZnO TFTs was examined to find out how the gate dielectric material, dielectric thickness, and operating temperature affect important electrical parameters such as drain current (I_D), field-effect mobility (µ_FE), subthreshold slope (SS), threshold voltage (V_Th), on/off current ratio (Ion/Ioff), drain conductance (g_d), transconductance (g_m), transconductance generation factor (TGF), and early voltage (V_EA). With SS = 0.396 V/dec, V_Th = 0.49 V, and µ_FE = 53.2 cm²/V·s, HfO₂ showed the best performance among the dielectrics under investigation. Improved characteristics were obtained by further optimization using a 120 nm HfO₂ layer: µ_FE = 54.2 cm²/V·s, V_Th = 0.27 V, SS = 0.315 V/dec, and Ion/Ioff ≈ 10¹¹. According to temperature-dependent analysis, device performance deteriorates at higher temperatures (> 400 K) because of increased trap effects and Fermi-level shifts, which lower mobility and result in threshold voltage instability. The potential of ZnO-based TFTs for high-performance analog and optoelectronic applications is highlighted by their optimal performance at room temperature. These results, which enable the extraction of analog FoMs pertinent to circuit designers, are based on a device model calibrated to experimental data and a methodical sweep of dielectric material, dielectric thickness, and operating temperature.