An Error-aware 4-2 Compressor Design for Balanced Accuracy and Efficiency in Approximate Multipliers

This paper presents an error-aware approximate 4-2 compressor design that enables a balanced trade-off between hardware efficiency and computational accuracy in approximate multipliers. The proposed design consists of two key components: a logic-simplified approximate compressor and a selective error compensation mechanism. The first component refines the Boolean expressions of an existing approximate 4-2 compressor to reduce area and power consumption. The second component introduces a lightweight correction circuit that targets high-probability error patterns, effectively minimizing the overall error distance. When implemented in a 32-nm CMOS technology, experimental results show that the proposed designs reduce area and power by up to 15% compared to existing approximate equivalents while achieving competitive accuracy metrics. The proposed multipliers are also applied to image processing and deep learning tasks to validate their practical benefits in error-resilient computing scenarios.