An Area-efficient Two-step Vernier Time-to-digital Converter with a Metastability-free Phase Detector for NAND Flash Memory Interfaces

This paper presents a low-power time-to-digital converter (TDC) designed for duty-cycle correction in NAND Flash memory interfaces. The proposed 5.5-bit two-step Vernier TDC integrates coarse and fine delay stages to support a wide timing range with compact implementation. A charge elimination circuit is incorporated into the true single-phase clocked (TSPC) sampling register to mitigate hold-time metastability with minimal area overhead. In addition, a twist power-gating (TPG) technique is applied to the delay chains to reduce leakage current with minimal impact on delay and performance. These techniques are suitable for multi-die memory systems requiring low standby current and compact layout. The TDC is fabricated in a 28-nm FD-SOI process using 150-nm thickoxide transistors to emulate NAND Flash interface conditions. Measurement results demonstrate a resolution of 3.64 ps at 100 MS/s and a power consumption of 0.9 mW. The core occupies an area of 0.0025 mm². The design achieves a balanced trade-off among resolution, power, and area, confirming its applicability to high-speed, lowpower memory interfaces.