Analytical Impact of Temperature on Ferroelectric Junction‐Less Surrounding‐Gate FET: Electrical Perspective

ABSTRACT This article presents a comprehensive temperature‐dependent analysis of Ferroelectric Junction‐less Surrounding‐Gate FETs (Fe‐JL‐SG FETs). To evaluate the effectiveness of ferroelectric integration, a detailed comparison between Fe‐JL‐SG FETs and conventional Junction‐less Surrounding‐Gate FETs (JL‐SG FETs) is carried out. Key device parameters—including surface potential, electric field, electron concentration, electron velocity, transconductance ( g m ), output conductance ( g d ), capacitance ( C GG ), cutoff frequency ( f t ), and I ON / I OFF ratio—are systematically investigated over a broad temperature range (100–500 K). The results demonstrate that Fe‐JL‐SG FETs exhibit superior electrical and analog performance with significantly reduced sensitivity to temperature variations compared to JL‐SG FETs. This enhanced behavior is attributed to the negative capacitance effect introduced by the ferroelectric material, which effectively reduces the subthreshold‐swing (SS) below the Boltzmann limit (60 mV/decade). However, this effect weakens as temperature increases. The simulation framework, developed using the ATLAS 3‐D device simulator, exhibits strong congruence with the proposed analytical model, thereby validating the theoretical constructs and reinforcing the predictive reliability of the developed approach.