An FVF-based Capacitorless LDO with Segmented Power Cells Achieving Fast Transient Response, Wideband High PSR, and Wide Load Current Range

This letter presents a capacitorless low-dropout (LDO) regulator with a flipped-voltage-follower (FVF) structure and segmented power cells, targeting fast transients and high power-supply-rejection (PSR). The design addresses the stability issues and bias point variations found in conventional FVF-based LDOs. Two key innovations are introduced: a cascode transistor in the fast loop to stabilize bias points, and a segmented core that extends the load current range and enhances AC performance. Additionally, this architecture enables efficient on-chip power delivery, reducing IR drop and simplifying power distribution networks. Implemented in 65-nm CMOS, the LDO operates from a 1.2-V input to a 1.0-V output, supporting a 100 mA load current. Simulations show a wideband PSR with a worst-case bound of < -14:2 dB and a transient response with undershoot and overshoot limited to 59 mV and 58 mV, respectively, for a 30 mA load step with a 10 ns edge.