Inverter‐Based Mixed‐Signal Low‐Dropout Regulator With Fast Transient Response

ABSTRACT In this paper, an example of the design of a switched‐capacitor without large off‐chip capacitor low dropout linear voltage regulator (SC‐LDO) based on bulk‐driven techniques and inverter as error amplifier is introduced. Compared with the traditional analog low‐dropout regulators, this circuit uses part of the switched‐capacitor circuit, which is completely composed of inverter. The structure is simple to implement, has a strong load capacity, and can work at low pressure with less static current. This low‐dropout (LDO) adopts SMIC 0.18‐m CMOS process for layout drawing and simulation. The simulation results show that the power supply voltage is 1.2 V, the static current is 8 A, the current efficiency is as high as 99.99%, and when the load current jumps from 1 mA with 1 ns time to 101 mA, the loop stabilization time is only 25 ns.