A Technical Survey of Sparse Linear Solvers in Electronic Design Automation

Sparse linear system solvers ([Formula: see text]) are foundational computational kernels in Electronic Design Automation (EDA), enabling the physical analysis of modern electronic systems. Applications from circuit simulation to full-chip power integrity and electrothermal analysis depend on these solvers to handle large-scale algebraic systems from Modified Nodal Analysis (MNA) or Finite Element/Volume Method (FEM/FVM) discretizations. With problem sizes escalating towards [Formula: see text] unknowns for next-generation designs [Ansys Inc. Ansys RedHawk-SC: Next-Generation SoC Power Noise and Reliability Signoff. White Paper (2022); D. Ren et al., A parallel iterative solver for scalable power grid analysis, Proc. ICCAD (2021) pp. 1–9] solver performance in terms of speed, memory, and scalability is a primary determinant of design cycle times. This paper provides a comprehensive technical survey of sparse solver paradigms in EDA, with three key contributions. First, we present a novel taxonomy that maps common EDA applications to their underlying matrix properties and most suitable solver classes. Second, we synthesize comparative performance data from recent literature to provide a quantitative, real-world basis for analyzing solver trade-offs. Third, we detail state-of-the-art advances and conclude with a forward-looking perspective on concrete research challenges, such as reinforcement learning for adaptive solvers and developing robust algorithms for mixed-precision, heterogeneous computing environments. An appendix provides a guide for reproducing a representative benchmark, enhancing the paper’s utility for researchers and practitioners.