Energy Efficient CMOS Stochastic Bit-based Bayesian Inference Accelerator

Stochastic computing-based Bayesian inference has emerged as a powerful approach for statistical computation, particularly in domains requiring high-dimensional probabilistic analysis. However, in conventional Von Neumann architectures, stochastic computing faces significant energy challenges due to the exponential growth of data volume associated with the Internet of Things (IoT). In this work, we proposed a CMOS stochastic bit-based Bayesian inference accelerator designed for energy-efficient stochastic computation. The stochastic bit in our design performs dual functions as both: 1) stochastic computation unit and 2) memory element, enabling an energy-optimized implementation of Bayesian inference. The proposed design is validated through a case study involving a 3-layer, 4-variable Bayesian network model, implemented using TSMC 65 nm GP process technology, with total energy of 1.5 nJ.