A PVT-stable 12-bit 800-MSPs pipelined SAR ADC with gain-enhanced gm-ratio amplifier

A 12-bit pipelined successive approximation register (SAR) analog-to-digital converter (ADC) is proposed, which operates at a sampling rate of 800-MS/s. With the assist of cross-coupled inverter pair, a gain-enhanced high-linearity open-loop residual amplifier (RA) based on gm-ratio achieves a high power efficiency and speed with complete steady-state and dynamic performance characteristics. The process, supply voltage, and temperature (PVT)-sensitive gain of RA is compensated by the adjustable bias current in the cross-coupled inverter pair. The prototype single channel ADC is integrated in an 8-channel time-interleaved ADC and implemented in a 28-nm CMOS process, which consumes 5.52 mW at 1-V supply voltage and 800-MS/s sampling rate. The measured inter-stage gain variation remains below 2% across a temperature range of -20-80 °C, achieving an SNDR and SFDR of 60.1 dB and 72.4 dB, respectively. The Walden figure of merit (FoM) is 8.35 fJ/conversion-step, and the Schreier FoM is 168.7 dB.