Design and evaluation of low-power 6T adiabatic PUF circuit

The adiabatic Physical Unclonable Function (PUF) utilizes adiabatic logic principles and CMOS process variations to achieve low energy dissipation and improved security for Internet of Things (IoT) applications. In this work, a low-power 6-transistor (6T) adiabatic PUF circuit is designed, and its performance is evaluated through simulation and chip measurements using a Rohm 0.18 µm CMOS technology. Simulation results indicate that the circuit achieves an average reliability of 98.93% under temperature variations, along with a uniqueness of 49.75% and an energy dissipation of 15.92 fJ per challenge cycle per bit when the bodies of the PMOS transistors are connected to Vdd. Furthermore, by eliminating one transistor and one phase of the power clock compared with the conventional low-power two-phase adiabatic design, the proposed circuit achieves a smaller implementation area while maintaining low-power dissipation. To verify the functionality of the design, a 4-bit chip was fabricated and tested. The measurement results demonstrate correct operation, with an average reliability of 96.92% at room temperature and a uniqueness of 51.67% with the body connected to Vdd.