Enabling scalable ferroelectric-based future generation vertical NAND flash with bonding-friendly architecture: strategies for erase and disturb optimization

We propose a novel ferroelectric VNAND (Fe-VNAND) architecture based on a TCAT (Terabit Cell Array Transistor) structure, integrating an amorphous IGZO channel and a band-engineered filler insulator for enhanced erase and disturbance characteristics. To overcome the limitations of poor hole transport in IGZO, a tailored erase (ERS) scheme employing stepped dummy word-line biasing is introduced, which effectively mitigates over-erasure at the bottom of the NAND string and enables reliable bitline sensing. By optimizing the doping overlap of the source line (<i>L</i> _OV) and operating the select word-line at low voltage (3 V), we demonstrate significantly reduced read disturbance and improved threshold voltage uniformity. Furthermore, the application of a band-engineered oxide/nitride filler structure enhances hole injection during ERS, leading to a 30% increase in memory window and a two-order-of-magnitude improvement in erase speed. Our findings suggest that the proposed structure and scheme are highly compatible with existing TCAT flows and scalable to future high-density ferroelectric memory systems. These innovations pave the way for energy-efficient, disturbance-tolerant 3D Fe-VNAND applicable to AI accelerators and edge computing platforms.