DNCM: efficient modeling of IC interconnect parasitic capacitance based on dual-net collaborative model

Robust and efficient quantification of interconnect parasitic capacitance stands as a cornerstone in VLSI circuit design, directly influencing the analysis of circuits’ delay and crosstalk. Considering the critical limitations of traditional parasitic capacitance pattern modelling methods-computational inefficiency and inadequate real-time performance, this paper proposes a dual-net collaborative modelling strategy. The presented solution, termed the dual-net collaborative model (DNCM), decomposes the modelling task into two synergistic components: a low-fidelity (LF) capacitance extraction model (referred as the trunk network) and an error prediction model (referred as the error-compensation network). The trunk network establishes the mapping relation between the parameterized variables of interconnect pattern and coarse-mesh simulation solutions. Meanwhile, the error-compensation network corrects the discretization-induced systematic errors by learning the residuals between the coarse-mesh and fine-mesh simulations. Through adding the LF capacitances predicted by the trunk network and their corresponding errors predicted by the error-compensation network, the high-fidelity (HF) capacitances can be obtained. The results show that the presented framework with dual networks can generate accurate predictions (achieve accuracy comparable to fine-mesh simulations) while substantially lowering the computational cost of data preparation relative to the traditional deep neural network (DNN).