Monolithic 3D IC Placement Using Reinforcement Learning

This dissertation explores reinforcement learning (RL)–based approaches to address placement challenges in monolithic three-dimensional (3D) integrated circuits (ICs). Placement in 3D ICs introduces unique constraints—such as inter-tier connectivity and volume limitations—that compound the inherent complexity of the already NP-complete 2D placement problem. To tackle these issues, this work proposes new algorithms that combine RL with simulated annealing (SA) for efficient design-space exploration and high-quality placement solutions. A framework for dynamic hierarchical cluster assignment is introduced to guide the transformation from 2D to 3D while preserving layout structure and reducing search complexity. The proposed methods are evaluated on a range of benchmarks, demonstrating improvements in wirelength and area metrics compared to baseline techniques. The results highlight the feasibility of integrating RL and machine learning techniques in electronic design automation for next-generation 3D systems. This dissertation is composed of a review book chapter, two peer-reviewed conference papers, and one journal paper under review. The introductory chapter explains the relationship between these contributions and situates them within the broader research context.