Energy Efficient Approximate Multiplier for Error Resilient Applications

Approximate computing is an emerging paradigm in computer arithmetic aimed at improving power efficiency by substituting exact computations with approximate ones in applications such as data analytics, deep learning, signal processing and image processing. This work aims to design an approximate multiplication circuit for error resilient applications. This paper proposes an approximation technique and error-correction scheme for unsigned binary multiplication. The approximate multiplier, which is proposed in this paper, is divided into three regions — two approximate and one exact where approximation using OR gates takes place both column-wise and row-wise. The partial product (PP) bits on the most significant bit (MSB) side on the first three rows are approximated in addition to the PP bits on the least significant bit (LSB) side using OR gates instead of exact computation using compressors, saving precious hardware resources. The error due to the approximate region is mitigated using a simple yet efficient error correction scheme. Multiplier designs are implemented using Verilog HDL and synthesized using TSMC 90[Formula: see text]nm process node. Hardware synthesis results indicate an improvement of up to 35% in the power-delay product (PDP) in the 8-bit circuit and an improvement of 59% in the 16-bit circuit compared to the existing designs without any significant compromise in the accuracy.