Bias Temperature Instability on SEE Susceptibility: Analysis on Combinational and Sequential Elements

This paper explores how Bias Temperature Instability affects the vulnerability of digital circuits to single event effects. The study assesses through circuit simulations the impact of BTI on the response of CMOS logic gates to heavy ions and neutrons, as well as the propagation of single event transients across logic levels in combinational logic. Additionally, it investigates the impact of aging on the Soft Error Rate, and latching window of a rising-edge flip-flop. Results show an increase in the SEE rate up to 47% induced by BTI and increased filtering capability for low values of collected charge.