A Simple Circuit Technique of Permeating Linear Tuning Law in CMOS OTA‐C Current‐Controlled Oscillator

This letter presents preliminary results on the evolution and application of a technique of infusing linear electronic tunability in CMOS OTA-C oscillators which involves a translinear squarer in the bias circuit of the OTA thereby making its transconductance a linear function of the external DC bias current. Therefore, it is seen that both CO and FO can be non-interactingly controlled in a fully uncoupled manner; the former through gm3 or gm4 and the latter through gm1 and/or gm2. Thus, the circuit realizes a quadrature voltage mode (VM) oscillator too. Equations (4) to (6) show that the modified circuit of Figure 1a is also capable of realizing a multi-phase (four-phase) oscillator in current-mode as depicted in the phasor diagram shown in Figure 1b. Thus, the oscillator circuit of Figure 1a is shown to be capable of realizing a quadrature oscillator in voltage-mode as well as a four-phase oscillator in current-mode. To the best knowledge of the authors, all these modes of operation together have not been claimed in any variants of this or any other known OTA-C oscillators [1-19]. It may be mentioned that the quadrature oscillators and multiphase oscillators have numerous applications in communication systems, signal processing, instrumentation, and measurement systems [19]. If this circuit is implemented by commercially available bipolar OTAs such as CA3080 or CA13600/13700, the transconductance of such OTAs is given by g m = I Bias 2 V T $$ {g}_m=\frac{I_{Bias}}{2{V}_T} $$ (where VT is the thermal voltage and IBias is the external bias current of the OTA) and therefore, if one chooses, g m 1 = g m 2 = g m = I Bias 2 V T $$ {g}_{m1}={g}_{m2}={g}_m=\frac{I_{Bias}}{2{V}_T} $$ ; the substitution of these values in Equation (2) results in Since f0 is directly proportional to IBias, therefore, a current-controlled oscillator (CCO) with a linear tuning law is obtainable in the case of the OTA-C oscillator of Figure 1a (as well as in all other OTA-C oscillators implemented earlier with bipolar OTAs, such as those in [13-19]). Since the CMOS technology is the prevalent technology for VLSI implementation, a number of researchers have implemented OTA-based oscillators using CMOS OTA architectures [3, 8-10, 12] which are either the same or some variant1 of the one shown here in Figure 2. Thus, it is seen that the linear tuning law is not feasible in this case, due to the dependence of each g m $$ {g}_m $$ on square root of I SS $$ {I}_{SS} $$ . In the next section, we present a simple modification of the basic architecture of the CMOS OTA of Figure 2, which circumvents this problem and facilitates the realization of a linear CMOS CCO from the oscillator of Figure 1a. The proposed modified CMOS OTA architecture is shown in Figure 3 which incorporates a current mode squarer2 as the additional circuit implemented from MOSFETs M 13 $$ {M}_{13} $$ to M 24 $$ {M}_{24} $$ in the basic CMOS OTA of Figure 2. The aspect ratios of the MOSFETs comprising the differential pair M1, M2, and the current mirror active load M3-M4 and the transistor M5 have been presently chosen by following the earlier works [10, 21-23]. Because of the limited scope of this communication, no effort so far has been made to optimize the choice of the aspect ratios of all the MOSFETs, which is left for future work. The quoted additional circuit is inspired by a MOS translinear multiplier proposed by Martin and Carlosena in [24], but has been augmented with additional MOSFETs to make it appropriate for the purpose intended here. The squarer circuit employed has a four-MOSFET translinear (TL) loop comprised of M14, M15, M16 and M17 along with a number of current mirrors (M3-M4, M5-M6, M18-M19 and M20-M21) and current repeaters (M7-M8-M9, M10-M11-M12 and M22-M23-M24) that ensure that the drain currents of the MOSFETs comprising the TL loop have appropriate values such that the application of the MOS TL principle [25] results in the creation of the output drain currents of MOSFETs M13, M17 being proportional to the square of the external bias current IBias. Thus, the tail current ISS of the differential pair M1-M2 has been made proportional to the square of the external DC bias current IBias. The evaluation of the performance of the proposed CMOS OTA of Figure 3, using SPICE simulations along with its layout and the consequent post-layout simulations, has been given in Appendix 1. Now f0 is directly proportional to IBias and therefore, a linear CCO has been attained which was not possible with the OTA-C oscillator of Figure 1a implemented with the conventional CMOS OTA of Figure 2. The proposed modified OTA of Figure 3 as well as the OTA-C oscillator of Figure 1a (using the conventional OTA of Figure 2 as well as the modified OTA of Figure 3) has been simulated in SPICE using 0.18 μm CMOS technology parameters with the aspect ratios of the various MOSFETs as given in Table 1 and all the OTAs biased with ±1.5 V DC power supply. Since ISS is equal to I Bias 2 4 I REF $$ \frac{I_{Bias}^2}{4{I}_{REF}} $$ , it follows that selection of IREF will affect the tunning range of IBias. However, the value of IREF has been finalized by observing the simulation results and finding for what value of IREF the best tunning range is obtained and accordingly, IREF was fixed as 25uA. The oscillator circuit has been simulated in SPICE by taking C1 = C2 = 10pf. To set/adjust the CO of the oscillator, the bias current IBias3 was taken to be 10.65 μA with IBias4 taken to be 10 μA. Figure 4a shows the transient response of the waveform generated by this circuit at bias currents IBias1 = IBias2 = 100 μA. Figure 4b demonstrates the voltage outputs V01 and V02. The SPICE-measured phase shift between the two waveforms has been found to be 92.35°, in excess of 180° (due to the negative sign in Equation (3)). These results confirm the quadrature behavior of the oscillator. Figure 4c demonstrates the four current output waveforms generated by the circuit of Figure 1a, which prove the correct workability of the circuit as a 4-phase current-mode oscillator. When the oscillation frequency was varied by varying IBias from 10 to 100 μA, the %THD of the waveform of V01 for different cases has been found to be within the range of 2.58% to 7.6% (with no amplitude stabilization circuit employed). From the simulations, the value of %THD has been found to be 7.6%, 6.6%, 5.2%, 4.29%, 4.03%, 3.61%, 3.12%, 3.02%, 2.90%, and 2.58% at the bias currents of 10, 20, 30, 40, 50, 60, 70, 80, 50, 60, 70, 80, 90, and 100 μA respectively. The phase noise of the quadrature oscillator, for the bias current of 100 μA (resulting in the operating frequency of 1.87 MHz) is shown in Figure 4d, from where it has been observed that for the frequency range of 10 kHz to 10 MHz, the phase noise of the oscillator in Figure 1a varies from 20 to −102.029 dBc/Hz. The frequency of oscillation of the generated waveform was found to vary from 1.28 to 3.95 MHz for the oscillator using the classical OTA of Figure 2 when ISS of OTA1 and OTA2 was varied from 10 to 100 μA. Note that as per Equation (11), if ISS is varied over one decade, f0 would vary in the ratio of 1: √10, namely, 1:3.16. A recheck of the earlier OTA-C oscillators realized with the CMOS OTA of Figure 2 or its variants, reveal that the tuning range of the various oscillators in [1, 2, 4] conforms to this expectation (see Table 2). On the other hand, for the oscillator of Figure 1 realized with the modified OTA of Figure 3, for the same range of bias current IBias of OTA1 and OTA2 (i.e., 10 to 100 μA), the observed frequency range was 0.18 to 1.87 MHz which matches well with the anticipated range of one decade, as per Equation (19). Current (10 μA to 100 μA) 0.18–1.87 MHz Since for the same range of the external DC bias currents, the two implementations of the same oscillator generate different ranges of oscillation frequencies, due to the different expressions for f0 (as in Equations (11) and (19) respectively), for a better comparison, a plot has been drawn for the normalized frequency f/fmin in both cases and the same is shown in Figure 4e. The plot of Figure 4e clearly validates the main contention of this communication. There is an abundance of OTA-C oscillators in the earlier technical literature [1-19] employing three or four OTAs, of which only the latter type provides fully uncoupled controls of the condition of oscillation as well as the frequency of oscillation. The OTA-C oscillators which belong to this category are those of [1-5], [7, 8] only. However, we have included in the comparison table only such oscillators, namely those of [1, 2, 4], where all the relevant data is available for comparison. From Table 2, it may be seen that the proposed oscillator of Figure 1a provides a larger tuning range, relatively larger frequency range of operation, operates at much reduced supply voltage and realizes a VM quadrature oscillator as well as current-mode 4-phase oscillator. However, % THD is a bit higher since no amplitude control scheme has been yet applied (which is left for future work as indicated in Section 5 of concluding remarks). In this communication, a simple circuit technique of modifying the architecture of the classical CMOS OTA has been presented by which its transconductance becomes directly proportional to the external DC bias current IBias which is otherwise proportional to I Bias $$ \sqrt{I_{Bias}} $$ . Therefore, when the proposed modified CMOS OTA architecture of Figure 3 is used to realize an OTA-C sinusoidal oscillator, it becomes possible to realize a linear CCO, which was not possible by realizing the same oscillator using the conventional CMOS OTA architecture of Figure 2. The validity of the realizability of a linear CCO by using the proposed technique has been verified from the SPICE simulation results. It, therefore, follows that with the introduction of the modified CMOS OTA architecture of Figure 3, all the previously known OTA-C oscillators from [1-19] and the references cited therein, which would provide a square-root type tuning law, that is, f O ∝ I Bias $$ {f}_O\propto \sqrt{I_{Bias}} $$ when implemented with conventional CMOS OTAs, can now be converted into linear CCOs provide f O ∝ I Bias . $$ {f}_O\propto {I}_{Bias}. $$ Further work is needed on (i) identifying the best squarer circuit, from among the many choices of squarer circuits available in technical literature [24], [25], to be employed in the suggested methodology (ii) the optimisation of the aspect ratios of the MOSFETs in the resulting linear CMOS OTA, with a view to increase its linear tunability range and (iii) the application of an appropriate AGC or feedback loop, to regulate the amplitude of oscillations and regulate THD and output swings in the CMOS OTA-C oscillator of Figure 1a. The authors wish to thank the Editor-in-Chief, Prof. Ahmed El Wakil, and the anonymous reviewers for their very useful feedback and constructive suggestions—all of which have been very helpful in preparing the revised version of the manuscript. The authors have nothing to report. The authors declare no conflicts of interest. The proposed modified linear CMOS OTA of Figure 3 has been simulated in SPICE using 0.18 μm CMOS technology parameters, with the aspect ratios of the various MOSFETs as given in Table 1, with all the OTAs biased with ±1.5 V DC power supply. Figure A1 (a) shows the variation of the simulated and theoretical transconductance values of the circuit of Figure 3. From this plot, the maximum deviation from linearity has been found to be about 5.56%. Figure A1 (b) shows the frequency response of the circuit from which the maximum operating frequency range of this circuit is found to be 36.07 MHz (flat bandwidth with the deviation in gm not more than 5%) at the DC bias current of 100 μA. The layout of the proposed circuit, made using Cadence Virtuoso software, is shown in Figure B1, from which the chip area is estimated to be (23.46*39.69) μm2 whereas the area of the conventional OTA of Figure 1 determined from its layout (not included to conserve space) is found to be (13.03*12.43) μm2. The various pre-layout and post-layout simulation results of the proposed circuit are given in Figure C1, which are found to be in good agreement with the corresponding pre-layout results. A comparison of the proposed CMOS linear OTA of Figure 3 with other previously known methods of designing linear CMOS OTAs/transconductors, based upon MOSFETs operating in saturation is given in Table A1. The authors testify that no new data have been generated through the research reported in this communication.