Low power and high-speed quadrate node upset tolerant latch design using CNTFET

Scalability, leakage, short-channel effects, and reliability problems are some of the difficulties facing the semiconductor industry as it continues to experience a reduction in size. Heavy charged particles striking an integrated circuit (IC) cause a Single Event Upset (SEU). As devices are scaled down, it usually causes Single and Multiple Node Upset. To overcome the upsets, device and CMOS circuit radiation hardening by design (RHBD) techniques are adopted. In the resent times, Carbon nanotubes have emerged as a feasible technology capable of addressing CMOS problems while maintaining performance and reliability. This manuscript proposes a Low power High speed Quadrate Node Upset Carbon Nanotube latch (LHQCNT). The LHQCNT latch contains three Dual Interlocked cells with a delta interconnection design, supplying enough redundant nodes to ensure robustness to Multi Node Upsets due to charge sharing. The investigation includes simulation, and performance comparison of a LHQCNT latch with an existing hardened latch. The LHQCNT latch obtained the power, delay, PDP and APDP as 4.4 µW, 1.23 ps, 5.41e-18 and 5.19e-2 respectively with a supply voltage of 1 V. Results from simulations show that the proposed LHQCNT latch archives low power, delay, and APDP of any latch with a comparable soft error tolerance level.