A Reconfigurable 11T SRAM Macro for Error Tolerance Content‐Addressable Memory and In‐Memory Computing

ABSTRACT With the explosive growth of global data volume, efficient matching and computation have become core requirements for data processing. Reconfigurable SRAM macro for content‐addressable memory (CAM) that realize rapid data matching and in‐memory computing (IMC) that reduce frequent data exchange between memory and computing unit is a promising new architecture for data efficient matching and calculation. However, during data matching using previous reconfigurable SRAM macro for CAM and IMC, errors in input data or information stored in memory can compromise the success of data matching. And in conventional reconfigurable SRAM macro for CAM and IMC, there is a widespread problem of short‐circuit current between the matching cells and the mismatching cells during data match operations, which impairs its energy efficiency. To address above problems, this paper proposes a reconfigurable 11T SRAM macro for error tolerance CAM and IMC. The proposed macro enables both exact matching and error tolerance matching, allows logic operations to be performed, and resolves the problem of short‐circuit current between the matching cells and the mismatching cells during data match operations. At a supply voltage of 1 V, our design achieves an energy consumption of 0.231 fJ/bit and a frequency of 515 MHz for exact matching, 1.249 fJ/bit and 462 MHz for error tolerance matching, and 25.47 fJ/bit and 489 MHz for logic computation.