A Scalable Ultra-Compact 1.2 kV/100 A SiC 3D Packaged Half-Bridge Building Block

This work presents a highly compact and scalable 1.2-kV SiC MOSFET half-bridge building-block module enabled by a die-integrated 3D PCB packaging technology. Compared with conventional DBC-based or TO-247-based SiC half-bridge modules, the proposed design reduces the physical volume and weight by more than 90% while maintaining full compatibility with standard PCB manufacturing processes. The vertically laminated DC+/DC− conductors and symmetric PCB–die–PCB stack establish a tightly confined commutation loop, resulting in a measured power-loop inductance of 2.2 nH and a 3.8 nH gate-loop inductance—representing up to 94% and 89% reduction relative to discrete device implementations. Because the parasitic parameters are intrinsically well-balanced across replicated units and the mutual inductance between adjacent modules remains extremely small, the structure naturally supports current sharing during parallel operation. Thermal and insulation evaluations further confirm the suitability of copper filling via high-Tg laminated PCB substrates for high-power SiC applications, achieving withstand voltages exceeding twice the rated bus voltage. The proposed module is experimentally validated through finite-element parasitic extraction and 950 V double-pulse testing, demonstrating controlled dv/dt behavior and robust switching performance. This work establishes a manufacturable and parallel-friendly packaging approach for high-density SiC power conversion systems.