Plasma-PEPSC D2.4 Report on Phase-1 Co-design with the EPI systems

Following the path started with the first WP2 deliverables (D.2.1 and D2.2), we continue to port and study the performance on the EPI architectures: Arm targeting SiPearl RHEA CPU, and RISC-V targeting the EPI long-vector accelerator. The remaining part of the text is structured as follows: In Section 1 we introduce scope of the deliverable and the co-design methodology, and in Section 2 we briefly describe the two EPI computational architectures. In Sections 3, 4, 5, and 6 we report on the studies and code optimizations performed on both Arm and RISC-V platforms respectively for the all codes BIT-1, Vlasiator, PIConGPU, and GENE/GENE-X. In Section 7 we briefly summarize the content of this deliverable, the