Analysis and Hardening of Combinational Standard Cells Against Transient Faults Using Device-Level Simulations

This paper presents hardened standard cells against transient faults using device-level 3D-TCAD simulation insights. First, at the device level vulnerable zones in common standard cells—including NAND, NOR, and INV cells—are precisely identified under different strike energy, angle, and location scenarios. Then, transistor-level hardened NAND, NOR, and INV cell designs are proposed based on the vulnerable zones from device-level investigations, achieving high resilience to faults. Finally, the proposed hardened designs are reevaluated extensively using both device-level and circuit-level simulations, demonstrating full immunity against SETs and high immunity against single-event multiple transients on adjacent cells. Compared to related hardening methods, the designs achieve a significantly lower probability of failure up to 94.8%, while incurring moderate overheads in terms of area and power consumption, and achieving improved delay. Our device-level analysis reveals that NAND cells exhibit the highest vulnerability to particle strikes, while among adjacent-cell combinations, NAND-INV pairs show the highest vulnerability to multiple transients. In contrast, NOR-INV combinations demonstrate the lowest vulnerability. These findings underscore the effectiveness of leveraging device-level insights to develop highly reliable designs for soft error mitigation in safety-critical applications.