Enhanced electrical stability of IGZO thin-film transistors using atomic layer deposited Al2O3/HfO2 dual-layer gate insulator

This study investigates the stability of positive bias temperature stress (PBTS) in bottom-gate indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) incorporating atomic layer deposited Al 2 O 3 /HfO 2 dual-layer gate insulators (GIs). By optimizing the thicknesses of the Al 2 O 3 and HfO 2 , hydrogen diffusion from the GI into the IGZO layer is effectively controlled and electron traps at the IGZO/GI interface are mitigated. The optimal dual-layer GI configuration for IGZO TFTs is identified as 15 nm Al 2 O 3 on 5 nm HfO 2 , resulting in an exceptionally low threshold voltage shift of −0.02 V under PBTS at 125 °C for 10 4 s. Additionally, the device exhibits excellent electrical performance, with a saturation mobility of 11.61 cm 2 /Vs, a subthreshold swing of 114 mV/dec, and a threshold voltage of −0.23 V. These results highlight the potential of IGZO TFTs with dual-layer GIs for advanced integrated circuit applications.

Institutions

Publication Details

Journal
Frontiers in Materials
Published
2025-12-12
DOI
https://doi.org/10.3389/fmats.2025.1735405
Primary Topic
Thin-Film Transistor Technologies
Type
article
Field-Weighted Citation Impact
0.00

Funders

Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Enhanced electrical stability of IGZO thin-film transistors using atomic layer deposited Al2O3/HfO2 dual-layer gate insulator

Frontiers in Materials
Thin-Film Transistor Technologies
article

Enhanced electrical stability of IGZO thin-film transistors using atomic layer deposited Al2O3/HfO2 dual-layer gate insulator

article en

Abstract

This study investigates the stability of positive bias temperature stress (PBTS) in bottom-gate indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) incorporating atomic layer deposited Al 2 O 3 /HfO 2 dual-layer gate insulators (GIs). By optimizing the thicknesses of the Al 2 O 3 and HfO 2 , hydrogen diffusion from the GI into the IGZO layer is effectively controlled and electron traps at the IGZO/GI interface are mitigated. The optimal dual-layer GI configuration for IGZO TFTs is identified as 15 nm Al 2 O 3 on 5 nm HfO 2 , resulting in an exceptionally low threshold voltage shift of −0.02 V under PBTS at 125 °C for 10 4 s. Additionally, the device exhibits excellent electrical performance, with a saturation mobility of 11.61 cm 2 /Vs, a subthreshold swing of 114 mV/dec, and a threshold voltage of −0.23 V. These results highlight the potential of IGZO TFTs with dual-layer GIs for advanced integrated circuit applications.

Frontiers in MaterialsVol. 12
Shandong University of Technology (CN), University of Manchester (GB), Southern University of Science and Technology (CN), Hanyang University (KR)
National Natural Science Foundation of China, Korea Basic Science Institute, Natural Science Foundation of Shandong Province, National Key Research and Development Program of China
Affordable and clean energy
Openalex Percentile: Top 44%
Thin-Film Transistor Technologies
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.