Harmonic Suppression and Circulating Current Mitigation in Parallel Active Power Filters Using Dual-Comparison One-Cycle Control

This paper presents a novel approach to reduce harmonic distortion and mitigate zero-sequence circulating current (ZSCC) in parallel active power filters (APFs). By employing Dual-Comparison One-Cycle Control (DC-OCC), this method effectively reduces harmonics. Carrier asynchronization among inverter modules in parallel configurations leads to the generation of ZSCC, which distorts output waveforms and reduces system efficiency. A mathematical model is developed to decompose ZSCC into low-, medium-, and high-frequency components, revealing how these components are influenced by carrier-phase deviations. Based on this model, a ZSCC extraction and compensation scheme is proposed. This method enables effective suppression of ZSCC without requiring additional components, communication links, or sensors. Simulation and experimental results demonstrate that the proposed approach achieves significant harmonic suppression, improved power factor, and a peak efficiency of 98.7%, confirming the effectiveness of the control strategy in practical applications.