Exploring Cache Policies on FPGA-Accelerated Simulations: Tradeoffs Between Usability and Simulation Speed

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Publication Details

Published
2025-09-28
DOI
https://doi.org/10.1145/3768617.3770732
Primary Topic
Embedded Systems Design Techniques
Type
article
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article

Exploring Cache Policies on FPGA-Accelerated Simulations: Tradeoffs Between Usability and Simulation Speed

Embedded Systems Design Techniques
article

Exploring Cache Policies on FPGA-Accelerated Simulations: Tradeoffs Between Usability and Simulation Speed

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Abstract

No abstract available for this paper.
Centre National de la Recherche Scientifique (FR), Université de Montpellier (FR), Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier (FR)
Openalex Percentile: Top 36%
Embedded Systems Design Techniques
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Exploring Cache Policies on FPGA-Accelerated Simulations: Tradeoffs Between Usability and Simulation Speed · (2025) | TGRS Research Map | TGRS