Impact van procesvariabiliteit op het falen van diëlektrica in nano-elektrische verbindingen

The reliability of Back-End-Of-Line (BEOL) interconnects is a critical challenge for the semiconductor industry, exacerbated by the use of low-k dielectric materials and continuous scaling of dimensions amidst persistent variability. Time-Dependent Dielectric Breakdown (TDDB) of BEOL dielectrics is identified as a major concern. To address this, this thesis presents a comprehensive and predictive TDDB modeling framework that accounts for both ideal and non-ideal dielectric geometries, enabling realistic lifetime estimation and design rule specification. The modeling strategy is developed in two stages. First, a supercell model is constructed to predict TDDB behavior in planar and idealized dielectrics. This model captures the statistical nature of breakdown driven by defect generation and critical defect density formation and is calibrated using experimental data from planar capacitor (p-cap) structures. With simulations, calibrations, and parameter extrapolations across different dielectric thicknesses, the model also enables accurate reliability predictions for a wide range of thicknesses. In the second stage, this model is extended to incorporate geometrical variability, such as line edge roughness (LER), tip shape variations, and via misalignment, through a novel shortest straight percolation path (SSPP) methodology. This enables the translation of local spacing distributions into breakdown statistics using weakest-link scaling principles. Geometrical variations are analytically linked to breakdown probability using integral formulations of the SSPP model. The mathematical derivation also reveals the interactions between multiple variability sources, identifying dominant failure mechanisms under specific geometric configurations. The result is a clear connection between process variability and local dielectric spacing, enabling prediction of geometry-induced reliability. Experimental analysis is also an integral component of this thesis. The newly performed measurements on design-representative structures including advanced SEM-based spacing analysis and a four-terminal ramped stress test to isolate tip-to-tip (T2T) breakdown provide clear evidence that geometrical variability impacts reliability. In addition, this work also incorporates reliability data from earlier experiments conducted by collaborators. These include line-to-line (L2L) and other BEOL structures, enabling broader model calibration and validation. The SSPP model shows nice agreement with measured breakdown time distributions across multiple structures and stress conditions. The variability-aware model developed in this research enables predictive determination of maximum tolerable process variations to meet BEOL TDDB reliability targets in future technology nodes. Critical specifications, including the maximum tolerable variations for lines, vias, and tips, are derived to ensure a 10-year product lifetime at operating conditions. Further analysis extends to advanced schemes such as air-gap and self-aligned via structures, demonstrating the model's flexibility and relevance for future BEOL technologies. In a nutshell, this thesis offers an experimentally grounded and physically informed modelling approach for BEOL TDDB, delivering actionable insights for reliability-aware design and process optimization in next-generation integrated circuits.