Scalable Embedded Parallel System With Implementation of Multi-node Encryption

The advancements in artificial intelligence (AI) and other innovative technologies promote a demand for high-performance processing systems, underscoring the importance of parallel computing. As a result, the application of parallel systems has spread across various domains. Most of the existing parallel systems are implemented on Field-Programmable Gate Arrays (FPGAs), which require complex designs and adjustments from the user and are often costly despite some performance benefits. This work explores an alternative approach by implementing a parallel system with a distributed memory protocol on affordable and commercially available microcontroller platforms to provide a scalable and cost-effective system. The proposed parallel system architecture contains a memory unit and a set of two or three processing nodes to increase hardware scalability. The design establishes an interconnected array of these modules to facilitate parallel computation. The implementation uses semaphores to enable process synchronization, identification, memory access control through a locking mechanism, and ID assignment. Encryption is used to demonstrate software scalability and the communication protocol of SPI connectivity. Each processing node executes computational tasks using encryption algorithms to convert input messages into encrypted text using the node’s localization and identification as keys. This setup showed increased efficiency compared to conventional single-core processors. However, the current software scalability architecture remains limited due to project time constraints, suggesting potential expansion in future research. Additionally, the proposed architecture can be expanded into three-dimensional arrangements, offering a promising approach to minimizing spatial requirements, substantially increasing scalability, and improving throughput by reducing data transmission distance.