Low quiescent current 110 nm capacitorless low dropout voltage regulator with wide load current range

Recent developments in Internet of Things (IoT), sensor-based mobile devices, implantable devices and smart wearables have fueled the demand for power-efficient and compact system-on-chip (SoC) solutions, causing power management in integrated circuit (IC) designs to become crucial. As low dropout (LDO) voltage regulators have become one of the key components in power management systems, capacitorless LDO (CLDO) voltage regulators are also becoming more popular due to their compactness which offers better power and cost-effectiveness compared to conventional LDO regulators. Power durability has become critical because longer battery life is highly preferred in portable devices, and this highlights the importance of minimizing the power consumption of the devices so that the battery discharges at a slower rate. An effective way to reduce the power in a CLDO regulator is to keep its current flow during idle mode, which is called the quiescent current, at a minimum level. This paper presents a low quiescent current CLDO regulator operating at a nominal voltage of 1.2 V with a regulated output voltage of 1 V utilizing the 110 nm CMOS technology. The proposed CLDO regulator achieved a low quiescent current of 5.18 µA with a wide range of load current up of 200 mA at maximum and 80% improved line regulation from the previous work with the same voltage requirements. The single-digit micro-ranged quiescent current greatly contributes in minimizing power consumption during the idle mode of the CLDO regulator which can be within single digit micro-Watt range where ultra-low power applications operate, thus prolonging the battery life, whilst the wide load range provides flexibility for the proposed CLDO regulator to power a larger range of circuits to drive with better line regulation and relatively good PSRR at low-frequency range.

Publication Details

Journal
Universiti Putra Malaysia Institutional Repository (Universiti Putra Malaysia)
Published
2024-12-02
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
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article

Low quiescent current 110 nm capacitorless low dropout voltage regulator with wide load current range

Universiti Putra Malaysia Institutional Repository (Universiti Putra Malaysia)
Analog and Mixed-Signal Circuit Design
article

Low quiescent current 110 nm capacitorless low dropout voltage regulator with wide load current range

article en

Abstract

Recent developments in Internet of Things (IoT), sensor-based mobile devices, implantable devices and smart wearables have fueled the demand for power-efficient and compact system-on-chip (SoC) solutions, causing power management in integrated circuit (IC) designs to become crucial. As low dropout (LDO) voltage regulators have become one of the key components in power management systems, capacitorless LDO (CLDO) voltage regulators are also becoming more popular due to their compactness which offers better power and cost-effectiveness compared to conventional LDO regulators. Power durability has become critical because longer battery life is highly preferred in portable devices, and this highlights the importance of minimizing the power consumption of the devices so that the battery discharges at a slower rate. An effective way to reduce the power in a CLDO regulator is to keep its current flow during idle mode, which is called the quiescent current, at a minimum level. This paper presents a low quiescent current CLDO regulator operating at a nominal voltage of 1.2 V with a regulated output voltage of 1 V utilizing the 110 nm CMOS technology. The proposed CLDO regulator achieved a low quiescent current of 5.18 µA with a wide range of load current up of 200 mA at maximum and 80% improved line regulation from the previous work with the same voltage requirements. The single-digit micro-ranged quiescent current greatly contributes in minimizing power consumption during the idle mode of the CLDO regulator which can be within single digit micro-Watt range where ultra-low power applications operate, thus prolonging the battery life, whilst the wide load range provides flexibility for the proposed CLDO regulator to power a larger range of circuits to drive with better line regulation and relatively good PSRR at low-frequency range.

Universiti Putra Malaysia Institutional Repository (Universiti Putra Malaysia)
Universiti Putra Malaysia, University of Kuala Lumpur, Universiti Kuala Lumpur
Affordable and clean energy
Openalex Percentile: Top 60%
Analog and Mixed-Signal Circuit Design
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