Design of integrated circuits for analog In-memory computing based on phase change memory

In the era of Artificial Intelligence (AI), numerous applications demand low-power computations involving large data volumes. Conventional digital computers face limitations due to the Von Neumann architecture, which necessitates continuous data transfers between memory and processing units. To overcome these constraints, novel computational approaches have been explored, including Analog In-Memory Computing (AIMC) based on resistive memory devices. AIMC has emerged as a promising non-Von Neumann solution for fast and energy-efficient Matrix-Vector Multiplication (MVM), a critical workload for deep learning inference. AIMC achieves substantial benefits in energy efficiency and speed by performing MVMs with O(1) time complexity. AIMC performs analog computations within resistive memory units by leveraging the physical properties of memory devices and exploiting Ohm’s and Kirchhoff’s laws. Phase-Change Memory (PCM) stands out for its ability to store multi-bit data long-term and its compatibility with CMOS fabrication processes. However, PCM devices face challenges such as non-linear I-V characteristics, random conductance drift, and variability in programmed cell states, which affect the accuracy of analog accelerators. This thesis explores these challenges and presents solutions for designing hardware accelerators using AIMC with PCM cells. Some hardware solutions are tailored to address PCM cell non-idealities but can be adapted for other AIMC systems. Results are supported by measurements from two prototype designs. The first prototype performs MAC operations with a computational architecture that includes reference cell conductance tracking (RCCT) to limit conductance drift effects on accuracy. The second prototype executes entire MVMs in one step, enhancing speed and power efficiency. Additionally, the thesis discusses a Bit Line Biasing circuit (BL-BC) designed to improve accuracy and energy efficiency, intended for a third prototype currently under fabrication. Finally, a programming procedure for PCM cells is presented to mitigate conductance drop and variability, involving current-induced heat-up to stabilize conductance, supported by experimental validation.