Hardware Implementation of Chaotic Image Encryption on FPGA

This paper proposes a new FPGA-based architecture for secure image encryption, utilizing chaotic maps for permutation and substitution mechanisms. Specifically, Duffing map is employed to generate permutation addresses, and the Henon map for value substitution; both techniques produce pseudo-random sequences with strong sensitivity to initial conditions. The hardware design implemented using Xilinx System Generator and deployed on an Artix-7 FPGA supports both grayscale and RGB image formats. A comprehensive performance analysis, utilizing Mean Squared Error, Histogram analysis, Correlation Coefficient Analysis, Number of Pixels Change Rate, and Unified Average Changing Intensity, demonstrates perfect image recovery and robust encryption resistance. The keys used in the encryption system are passed using the NIST STS randomness test. The single-round and multi-round designs deliver a processing acceleration ranging from 2.11 to 3.92 for image sizes 128×128 to 1024×1024 pixels, highlighting their effectiveness and practicality for real-time encryption in low-latency environments.