Ontwerp van variatiebestendige digitale circuits met extreem lage voedingsspanning

In the proposed research we will further investigate ultra low power digital circuit techniques. The focus will be on in-situ timing detection with automatic error correction and/or prevention for further power reduction in digital circuits. It also entails the verification of the results with silicon prototypes in advanced CMOS technologies. The techniques that will be studied and further developed should be compatible with the standard digital design flows.