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The main goal of this PhD research was to investigate the design and testing process of high-speed CMOS circuits for future high-energy physics (HEP) experiments systems expecting total ionizing dose (TID)-resilience of 1 Grad. The work concentrates on the analysis of circuits to extend the radiation robustness and performance in the context of the radiation-tolerant high-speed transmitter (HST). This work shows the design considerations and analysis of radiation-tolerant high-speed flip-flop circuits, duty cycle corrector (DCC), and the implementation of a 25.6 Gbit s–1 radiation tolerant high-speed serializer in 28 nm bulk CMOS that is incorporated in the Demonstrator ASIC for radiation- tolerant transmitter in 28 nm CMOS (DART28) HST chip developed in the context of the CERN R&D program. For a better understanding of the study's challenges, the thesis introduces the subject of particle interactions with matter in the context of the radiation effects in CMOS circuits, including long-term degradation effects as well as short-term effects caused by the passing particles. The mitigation techniques against ionizing radiation effects are discussed, showing the benefits and drawbacks of their implementation. The studies analyze various types of flip-flops, especially their performance and radiation robustness. The sensitivity to the leakage current of the high-speed true single-phase-clock (TSPC) circuits limiting their minimum operating frequency, even to levels of multiple GHz, depending on the process voltage temperature (PVT), is analyzed. Furthermore, the TSPC flip-flop with the adopted mitigation strategy makes the circuit insensitive to the leakage current. When compared to the standard TSPC and static master-slave architecture, it demonstrates advantages in performance, power efficiency, and radiation tolerance, highlighting the benefits of incorporating mitigation into TSPC design. The radiation-aware transistor model, based on the raw transistor irradiation data, was developed to estimate the influence of radiation on these circuits. The DCC based on the digitally controlled current-starved inverters is shown in the context of limiting the even-odd jitter (EOJ) in a high-speed serializer by controlling the duty cycle of the clock. The designed circuit, consisting of the duty cycle adjustment (DCA), duty cycle measurement (DCM), and digital control logic, provides tunability of ±4.7 ps with resolution below 200 fs, making it suitable to suppress the EOJ of high-speed serializers, thereby extending their TID-tolerance. Finally, as an application of the developed radiation-tolerant circuits, a high-speed serializer operating at the data rate of 25.6 Gbit/s-1 was designed and incorporated in the HST of the DART28 chip. The serializer is a multistage circuit, serializing data from 640 parallel data streams at 40 Mbit/s to the serial data stream at the nominal data rate. The circuit provides three taps at a nominal data rate required for the generation of the feed-forward equalization (FFE) signals in the driver circuit to overcome bandwidth limitations. The serializer circuit uses the designed TSPC circuits protected against leakage current influence to ensure high speed of operation and timing margins high enough to ensure correct operation even at ultra-high doses. Moreover, the DCC was used to counteract the radiation-induced duty cycle changes of the high-speed clock (12.8 GHz), limiting the radiation-induced increase of the EOJ. The DART28 serializer is a triple modular redundancy (TMR) design with the capability of disabling that protection in favor of lower power consumption of the circuit. Moreover, the ability to generate FFE taps can also be disabled. That reconfigurability of the circuit results in the power consumption varying from 34 mW to 64 mW depending on the mode of operation. The irradiation campaign showed that the designed serializer could sustain doses exceeding 2 Grad, which is several times higher than the current state-of-the-art. During the heavy ion campaign, the single event effect (SEE)-immunity in different modes of operation was assessed, showing a significant improvement coming from the applied TMR strategy, reducing the number of errors by at least one order of magnitude.