Evaluating IEC 61499 based Systems on FPGAs

IEC 61499 is an industrial standard for distributed systems, which is based on Function Blocks (FBs). Communication between them is divided into data and events, and only when an event occurs corresponding data is processed. This allows that FBs work in parallel and can be distributed over several different devices. Despite the parallelism of the design seems to fit perfectly for Field Programmable Gate Arrays (FPGAs), only a few studies have been published on the topic. Although all of them report an increase of execution speed, no general analysis of the cause was made. In addition, the effort and complexity of writing an IEC 61499 based design for FPGAs was never considered. This work presents a novel approach to comparing the different programming styles used in IEC 61499 and Very High Speed Integrated Circuit Hardware Description Language (VHDL) and highlights the benefits and problems about porting such IEC 61499programs to FPGAs. To do so, widely used and accepted program metrics are adjusted and then applied to evaluate various aspects of different implementations. The adapted Cyclomatic Complexity and Halstead’s software metrics can be used to compare the fundamental different programming languages: C++, VHDL, and IEC 61499 based programs. Meaningful data are acquired by writing programs in VHDL and for a IEC 61499based solutions of common tasks. The open source 4diacTM IDE is used to design IEC 61499 based solutions. With the internal code generator the system is converted to C++ code executable in 4diacTM runtime environment (FORTE). An additional code generator based on [1] is implemented and used to generate VHDL code. A third native VHDL implementation is used to compare the generated programs with a hand-optimized solution. Comparison of execution speed shows that an FPGA solution is twice as fast as the C++ implementation. As expected, the hand-tailored solution is even faster by a factor of six. The results of the Cyclomatic Complexity analysis show that native VHDL programs and a IEC 61499 based systems are similar. Due to the ambiguity of the Cyclomatic Complexity, small deviations can be found. This observation is expected as the result presents the number of independent program paths and both implementations are the solution of the same problem. The main downside of native VHDL programs is that the effort is much higher. Depending on the task and the interpretation of the results, the effort increases between a factor of two and ten. The lower design effort of IEC 61499 based systems shows that it is beneficial to use such systems. With a code generator, porting such systems to FPGAs can be done automatically with minimal additional effort. This study provides methods to compare results of different code generators pinpoints the downside of the used one; the dramatically increased program size. To improve this characteristic, it is suggested to buffer only events without corresponding data, similar to FORTE.