Study on HILS Implementation of FPGA-Based PFC Circuits Using Sub-Cycle Average Models

This paper presents a Field-Programmable Gate Array (FPGA)-based Hardware-in-the-Loop (HIL) simulation of an Interleaved Boost Power Factor Correction (PFC) converter using the Sub-Cycle Average (SCA) modeling technique. The main objective is to achieve accurate real-time simulation performance given the hardware constraints of low-cost FPGAs. By combining the SCA modeling approach with a time-averaging correction method, the proposed model effectively reduces sampling delays and duty-cycle estimation errors arising from asynchronous Pulse Width Modulation (PWM) signal acquisition. The SCA-based converter model and time-averaging correction technique were implemented in MATLAB/Simulink R2024b using the HDL Coder environment. To validate real-time simulation accuracy, power factor improvement was evaluated for a two-phase Interleaved Boost PFC operating at a switching frequency of 60 kHz. Experimental results confirm that the proposed approach enables accurate Controller–HIL testing of power converters, even when implemented on low-cost FPGA platforms such as the Zybo Z7-10 evaluation board.