Integration of the AES cryptography extension into a RISC-V architecture

The purpose of this project is to implement the ratified cryptographic extension in the pre-existing RISC-V processor design, CORE-V Wally. One of the most common and robust forms of cryptography is the Advanced Encryption Standard (AES). This algorithm contains many rounds of substitution and permutations using a key to ensure secure encryption/decryption. In most modern CPUs, such as AMD and Intel, their Instruction Set Architecture (ISA) supports a form of cryptography, usually AES, to provide security for private and sensitive data. Incorporating a hardware AES module into a processor also serves to increase its efficiency and security. Software-based approaches to installing cryptographic algorithms on a computer are significantly slower because many hardware-based designs include specialized instruction sets for AES and the ability to run on machine-level language. Using hardware-based AES adds another layer of protection by removing the risk of side-channel attacks that could affect software on a machine. For the RISC-V process, the integration of ISA-supporting cryptography would serve the same purpose, where the AES algorithm will perform more efficiently and securely due to the specialized and ratified instruction set detailed by the RISC-V organization. This implementation can pass the regression tests to completely verify that CORE-V Wally will have cryptographic capabilities. Unlike the specifications detailed by the RISC-V organization, this implementation combines certain instructions into a unified module to reduce the total area required for the AES cryptography extension.