PERFORMANCE EVALUATION OF NEORV32 RISC V PROCESSOR USING FREERTOS TRACE DRIVEN CACHE SIMULATION

In increasingly complex embedded systems, optimizing memory hierarchy is crucial to attaining high performance and energy efficiency. This thesis uses execution traces from FreeRTOS workloads that mimic realistic multitasking behavior to analyze the cache subsystem of the NEORV32 RISC-V softcore processor. To simulate adaptable architectures with different cache sizes, associativity, block sizes, prefetch depths, and replacement/write policies, a C++ trace-driven cache simulator was created. Single-level, two-level, and prefetch-enabled hierarchies were among the eight cache configurations that were assessed. According to the results, adding an L2 cache decreased main-memory traffic by almost 40%, while increasing associativity from direct-mapped to 2-way decreased L1 miss rates by roughly 19%. Access latency was further reduced by about 35% with the implementation of moderate prefetching. In comparison to the baseline, the top-performing configuration—32 B block, 2-way L1, 12 KB 6-way L2, and tuned prefetch achieved a 90% reduction in memory traffic and an effective 97% reduction in miss-rate. All things considered, these results highlight how latency is reduced, and bandwidth is maximized by striking a balance between hierarchy depth, associativity, and prefetch aggressiveness. A useful tool for cache optimization and performance analysis in RISC-V-based embedded systems is provided by the suggested trace-based simulation framework.