A dual-network centralized control system for Elettra 2.0

The Elettra 2.0 storage ring, scheduled for commissioning in 2026, introduces a novel control system architecture, departing from distributed front-end computers. High processing power and intelligent devices, such as magnet power converters, beam position monitors, beam loss monitors, low-level RF systems, and fast interlocks, support centralization. These devices connect through a dual-network design: a standard Ethernet link, managed by virtual servers running Tango, handles supervision, while a high-speed fibre-optic link with custom protocols enables real-time control. Fast interfaces feed a centralized, multi-core real-time (RT) server, where hardware partitioning and the Data Plane Development Kit (DPDK) allow low-latency processing up to 1.1 MHz. Conceptually, each core mimics a front-end computer, while the server’s RAM acts as a high-speed communication bus minimizing delay and latency. This architecture simplifies the infrastructure, improves scalability and enables advanced machine-wide control, ensuring reliability for next-generation accelerators.

Publication Details

Journal
JACOW
Published
2025-12-05
DOI
https://doi.org/10.18429/jacow-icalepcs2025-thpd002
Primary Topic
Particle Accelerators and Free-Electron Lasers
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

A dual-network centralized control system for Elettra 2.0

JACOW
Particle Accelerators and Free-Electron Lasers
article

A dual-network centralized control system for Elettra 2.0

article en

Abstract

The Elettra 2.0 storage ring, scheduled for commissioning in 2026, introduces a novel control system architecture, departing from distributed front-end computers. High processing power and intelligent devices, such as magnet power converters, beam position monitors, beam loss monitors, low-level RF systems, and fast interlocks, support centralization. These devices connect through a dual-network design: a standard Ethernet link, managed by virtual servers running Tango, handles supervision, while a high-speed fibre-optic link with custom protocols enables real-time control. Fast interfaces feed a centralized, multi-core real-time (RT) server, where hardware partitioning and the Data Plane Development Kit (DPDK) allow low-latency processing up to 1.1 MHz. Conceptually, each core mimics a front-end computer, while the server’s RAM acts as a high-speed communication bus minimizing delay and latency. This architecture simplifies the infrastructure, improves scalability and enables advanced machine-wide control, ensuring reliability for next-generation accelerators.

JACOW
Industry, innovation and infrastructure
Openalex Percentile: Top 47%
Particle Accelerators and Free-Electron Lasers
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.