Modernizing software and hardware for LANSCE EVR with FPGA and Real Time Linux

This paper describes the approach to modernizing Los Alamos Neutron Science Center’s (LANSCE) Event Receiver (EVR) by replacing the Micro Research Finland (MRF) EVR with Xilinx UltraScale+ Multi-Processor System on a Chip (MPSoC). The Xilinx UltraScale+ MPSoC architecture has been chosen for this project due to its use by other teams across LANSCE and around the industry. The EVR modernization project will utilize open-source FPGA design, mrf-openevr, along with in-house implementations for interfacing. The EVR will: produce timing patterns from Event Generators (EVG) via an event link within existing time constraints, manage new and reoccurring entries into the Per Cycle Data Buffer (PCDB), and provide diagnostic tools in an easy-to-use Real Time Linux interface. The EVR modernization project is in the evaluation stage where minimum viable product criteria is being evaluated on development boards. LA-UR-25-24009