Low-Power Analog Circuit for Learning Vector Quantization-Based Brain Tumor Classification Using CMOS 45 nm Technology

This study proposes a power-efficient analog design methodology for implementing the learning vector quantization (LVQ) algorithm using 45 nm CMOS technology in the Cadence design environment. The architecture is built around a highly optimized Euclidean distance circuit (EDC), supported by current mirrors (CM) for accurate current replication and a loser-take-all (LTA) circuit for final classification. Designed to operate at an ultralow supply voltage of 0.3 V, the system significantly reduces power consumption while maintaining high computational performance. The proposed design is validated through extensive Cadence-based simulations in the context of brain tumor classification, achieving a classification accuracy of 97%. Results demonstrate the effectiveness of the approach in delivering accurate and energy-efficient analog computation. Comparative analysis further confirms its superiority over existing techniques in terms of both power efficiency and classification reliability, making it well-suited for low-power, edge-based biomedical applications.