Prototyping of SSD and SSD controller.

The subject of the research is the process of designing and developing an efficient SSD controller, including testing and studying its performance. The limitations of the traditional approach using computer modeling are considered, which are caused by the complex structure of SSD controllers and the peculiarities of the physical characteristics of memory chips. The main object of study is the creation of a physical prototype of an SSD controller and SSD drive based on the Zynq system-on-chip, allowing for comprehensive testing and verification of the device's functionality in real operating conditions. The limitations and advantages of using programmable logic integrated circuits for prototyping solid-state drives are discussed. The research aims to enhance the performance and reliability of solid-state drives by introducing new methods for testing and assessing the performance of controllers and memory during the development stage. The research method involves creating a hardware physical prototype of an SSD controller and solid-state drive based on Zynq. The scientific novelty of this research is defined by the development of a methodology for creating a physical prototype of an SSD controller and SSD drive based on the Zynq system-on-chip, designed for detailed evaluation of the controller's performance. Traditional computer modeling has a number of limitations due to insufficient consideration of the physical characteristics of modern NAND Flash chips. The creation of a physical prototype allows for the elimination of this drawback, providing a detailed implementation of the SSD controller logic while accounting for the interaction and behavior of real memory. The proposed approach focuses on using development boards from the Zynq family, featuring an integrated ARM processor and FPGA, which enables flexible and comprehensive design, closer to actual operating conditions. The practical stages of development and adaptation of the prototype are described in detail, including the selection of appropriate memory chips and interfacing them with the used platform. The results obtained demonstrate significant potential for the proposed methodology to reduce development time and improve the quality of next-generation SSD controller development, which is particularly relevant in the context of growing market demands for performance and reliability of data storage devices.