Performance Evaluation Metrics for Optimized DSP Architectures: Benchmarking methods to assess speed, power, and resource utilization

This study presents a comprehensive performance evaluation of optimized Digital Signal Processor (DSP) architectures using benchmarking methods designed to assess computational speed, power efficiency, and resource utilization. The objective is to establish standardized metrics for quantifying improvements achieved through instruction-level optimization, parallelism, and low-power design techniques in modern DSP systems. Experimental evaluations were performed using three benchmark applications—Finite Impulse Response (FIR) filtering, Fast Fourier Transform (FFT), and Matrix Multiplication—executed on both conventional and optimized DSP cores. The optimized architecture employed a reduced instruction set with pipelined arithmetic units and clock gating mechanisms for dynamic power control. Results revealed a 32.6% improvement in execution speed, a 27.4% reduction in power consumption, and a 21.8% decrease in logic resource usage (LUTs) compared to the baseline architecture. The analysis also integrated performance-per-watt (PPW) and million instructions per second per watt (MIPS/W) as composite efficiency indicators, demonstrating that the optimized DSP achieved a PPW value of 1.32×10⁶ and a MIPS/W ratio improvement of 38.5%. Benchmarking data were validated using a Xilinx Zynq-7020 FPGA test platform and MATLAB/Simulink simulation for algorithmic verification. These findings confirm that a well-defined metric framework—combining speedup ratio, energy efficiency, and hardware resource indices—provides a holistic assessment of DSP architecture performance. The proposed benchmarking methodology enables comparative analysis across diverse DSP designs, guiding future development in energy-aware and high-performance signal processing systems.