Using a Shadow Mask during Gas-Phase Etching: A One-Step Patterning Method for Poly-Silicon Layers

This paper presents a convenient poly-silicon layer patterning technique, using a shadow mask during a gas-phase etching process. The etching is carried out at atmospheric pressure and delivers high throughput, single side processing and high selectivity, preserving the mask for multiple use and with potential for industrial application. This work was carried out in the context of the development of solar cell architectures beyond the standard TOPCon, where more sophisticated etching steps are required to accurately pattern poly-silicon layers across the wafer surface, in particular for the application of back contacted cells.

Publication Details

Journal
EU PVSEC
Published
2025-11-20
DOI
https://doi.org/10.4229/eupvsec2025/1bo.3.4
Primary Topic
Silicon and Solar Cell Technologies
Type
article
Field-Weighted Citation Impact
0.00
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article

Using a Shadow Mask during Gas-Phase Etching: A One-Step Patterning Method for Poly-Silicon Layers

EU PVSEC
Silicon and Solar Cell Technologies
article

Using a Shadow Mask during Gas-Phase Etching: A One-Step Patterning Method for Poly-Silicon Layers

article en

Abstract

This paper presents a convenient poly-silicon layer patterning technique, using a shadow mask during a gas-phase etching process. The etching is carried out at atmospheric pressure and delivers high throughput, single side processing and high selectivity, preserving the mask for multiple use and with potential for industrial application. This work was carried out in the context of the development of solar cell architectures beyond the standard TOPCon, where more sophisticated etching steps are required to accurately pattern poly-silicon layers across the wafer surface, in particular for the application of back contacted cells.

EU PVSEC
Industry, innovation and infrastructure
Openalex Percentile: Top 48%
Silicon and Solar Cell Technologies
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Using a Shadow Mask during Gas-Phase Etching: A One-Step Patterning Method for Poly-Silicon Layers · EU PVSEC (2025) | TGRS Research Map | TGRS