Exploring Thermal Runaway in Analog Accelerators for In-Memory CNN Computing

Processing-in-Memory (PIM) is a technology that integrates computing units directly into memory, enabling data processing at its source. This approach significantly reduces data movement and enhances computational efficiency, making PIM a promising solution for tasks that involve large volumes of data movement, such as Convolutional Neural Networks (CNNs). However, when computing units are deployed in 3D memory, the additional power consumed by computing units can significantly increase the temperature of the DRAM die, accelerating the current leakage of DRAM cells. As a result, DRAM needs to refresh more frequently to ensure data integrity. This extra refresh power consumption further increasing the die temperature, creating a positive feedback loop leading to thermal runaway conditions. Consequently, DRAM die has to operate under a critical temperature to avoid thermal runaway through throttling or dynamic voltage and frequency scaling (DVFS). In this paper, we investigate the thermal runaway problem in PIM accelerators. We begin by proposing a novel analog PIM accelerator architecture. We then conduct a detailed power analysis and thermal simulation of a 3D DRAM stack to determine the system's operating temperature. This temperature is used to adjust the DRAM refresh cycle, which in turn influences power and thermal characteristics in an iterative loop. The process continues until the system reaches either a thermal steady state or experiences thermal runaway. Through this analysis, we identify the critical temperature threshold at which thermal runaway occurs for the proposed accelerator, under varying 3D DRAM stack heights in in-memory computing environments.