Design and Simulation of Low-Power Adiabatic PUF Circuit

The rapid development of Internet of Things (IoT) devices has raised challenges in hardware security, as these devices often transmit sensitive data. Physically Unclonable Functions (PUFs) provide a promising approach to address such security concerns. However, high power consumption limits the efficiency of PUFs and reduces battery life in IoT devices, making low-power operation essential while generating secure keys. Adiabatic logic offers a method to reduce energy dissipation in CMOS circuits. By combining these concepts, adiabatic-based PUFs utilize both CMOS process variations and adiabatic logic principles to achieve low-power operation while maintaining high security. In this paper, a low-power 6-transistor (6T) adiabatic PUF circuit is designed and evaluated through simulation using 0.18 μm CMOS process. The simulation is performed under three body-bias conditions, where the PMOS transistor body is connected to Vdd, Vpc, or the source, and the results show that the proposed PUF achieves high key metrics including reliability and uniqueness close to their ideal values. In addition, it achieves an energy dissipation of 15.10 fJ/Cb-cycle per bit, reducing energy dissipation by over 60% compared to the conventional quasi-adiabatic design. Furthermore, by reducing the number of transistors compared to the conventional ultra-low-power design, the proposed circuit achieves a smaller implementation area.