A Study on Error Correction for Domain Wall Motion Memory

Vertical domain wall motion memory, which uses magnetic pillars composed of artificial ferromagnets with diameters of several tens of nanometers, is gaining attention as a next-generation high-capacity memory solution. In this memory device, where domain walls move vertically, deletion and insertion errors can occur due to fluctuations in domain wall displacement, which are influenced by the write and drive currents. In this study, we construct a read/write (RW) channel model incorporating probabilistic domain wall motion memory with a 512-bit pillar structure and evaluate an error correction system using a Levenshtein code concatenated with a Reed–Solomon (RS) code. The results show that, in the scheme where each pillar is divided into prespecified blocks and Levenshtein coding is applied, the frame error rate performance improves as the number of blocks increases. Furthermore, it was found that the decoding can achieve the frame error rate (FER) less than 10-3 when the standard deviation of domain wall displacement variation is reduced to 0.042 or lower.