Recent progress of vertical GaN-on-Silicon devices

Although qualified up to 650 V voltage operation, lateral GaN devices are subject to severe limitations for higher voltage applications such as a large device size, surface trap related reliability concerns or the absence of avalanche breakdown due to the peak electric field at the gate vicinity. This led to vertical GaN development, which is under extensive investigations worldwide as all the above-mentioned issues could be cured. State-of-the-art vertical GaN devices are fabricated on bulk GaN substrates, thanks to the high quality of the substrates in terms of low dislocation density and low impurity concentrations. However, they are prohibitively expensive, and only rather small area substrates are available. In this talk, we will describe the current status of GaN-based fully vertical devices grown on large diameter silicon substrate with a particular focus on ongoing efforts in this domain, which are part of the EU-funded YESvGaN project. Despite the common belief about the limited drift layer thickness or wafer diameter due to the large mismatch in coefficient of thermal expansion (CTE) between Si and GaN, we will show that a local substrate removal with suitable related growth and process optimization enabled outstanding initial achievements such as extremely low on-resistance in 1200 V-class fully vertical pn diodes with avalanche breakdown capability. Furthermore, the enhancement of the mechanical robustness of the resulting membranes during the fabrication process enables the implementation of a heat sink based on thick Copper and consequently high on-state current spreading well-above 10 A. It can be pointed out that preliminary fully vertical transistors have been successfully developed, paving the way for further advancement in this field.