Optimized Reversible Parity-Preserving Multiplier Circuits in Nanotechnology

Reversible logic, as one of the new technologies, plays a significant role in designing quantum computers due to the absence of energy loss, as well as using reversible circuits in low-power CMOS circuits, quantum calculations, and DNA computing. Multipliers are among the most critical circuits in computer calculations. This study proposes an optimized unsigned and signed reversible parity-preserving multiplier circuit. In addition, this study seeks to present a reversible block, as well as reversible signed and unsigned multiplier circuits using the presented block and the proposed design. The presented circuits reduce the quantum cost and are considered parity-preserving. In order to utilize the designs presented in variable sizes, two circuits in n×n sizes are provided. Further, a number of equations are presented to calculate the quantum costs, along with the number of constant inputs and garbage outputs in the proposed circuits.