Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication

This study presents the Cartesian Accumulative Matrix Pipeline (CAMP) architecture, a novel approach designed to enhance matrix multiplication in Vector Architectures (VAs) and Single Instruction, Multiple Data (SIMD) units. CAMP improves processing efficiency of Quantized Neural Networks (QNNs). Matrix multiplication is a cornerstone of machine learning applications, and its quantized versions are increasingly popular for more efficient operations. Unfortunately, existing VAs and SIMD-support units struggle to efficiently handle these quantized formats. In this work, we propose CAMP, a simple yet effective architecture that leverages a hybrid multiplier. The CAMP architecture significantly advances the performance of vector architectures in handling quantized data, enabling more efficient execution of matrix multiplication across various platforms, specifically targeting the ARMv8 Scalable Vector Extension (SVE) and edge RISC-V with SIMD-support unit architecture. Thanks to its hierarchical design, CAMP natively supports multiple integer precisions; here we focus on 4-bit and 8-bit, while the unit remains applicable as a general-purpose integer multiplier across other bit widths. In addition to increasing throughput, CAMP’s architectural design also contributes to energy efficiency, making it an effective solution for low-power applications. Evaluations on a range of Large Language Models (LLMs) and Convolutional Neural Networks (CNNs) demonstrate that matrix multiplication operations using the proposed micro-architecture achieve up to 17 × and 23 × performance improvements compared to their respective baselines, the ARM A64FX core and a RISC-V-based edge System-on-Chip (SoC). Furthermore, synthesis and place-and-route (PnR) of the CAMP micro-architecture — using Synopsys ICC2 for the ARM TSMC 7nm (A64FX) and Cadence Innovus for the GlobalFoundries 22nm flow (RISC-V SoC)—add only 1% and 4% area overhead, respectively, compared to the baseline designs.