Insights Into the Effects of Interface Trap Charges on Electrostatic-Based Magnesium Silicide Tunneling Interface

This work presents an in-depth analysis of a newly proposed electrostatically doped magnesium silicide Tunnel FET (ES-Mg2Si-TFET), developed to overcome key limitations in traditional TFET architectures. Conventional designs suffer from inadequate ON-state current (ION) and sensitivity to random dopant fluctuations, both of which hinder their viability in ultra-low power electronics. To address these constraints, the ES-Mg2Si-TFET leverages a dual strategy involving dielectric modulation and source region optimization. Numerical simulations reveal a substantial enhancement in device performance, with ION increased by nearly five orders of magnitude and subthreshold swing (SS) improved by 89% relative to conventional counterparts. Furthermore, the influence of interface trap charges (ITCs) on device stability is thoroughly investigated. Results show that the ES-Mg2Si-TFET maintains better immunity to ITC-induced flat-band voltage shifts compared to standard electrostatically doped TFETs. These advancements in both static and analog/RF figures of merit under low-voltage conditions establish the ES-Mg2Si-TFET as a strong contender for future energy-efficient integrated systems.