Evolution of Gate-Oxide Interface Traps in Planar SiC MOSFET Under Repeated Short-Circuit Stress

This article investigates the evolution of gate-oxide interface traps in planar SiC MOSFETs under repeated short-circuit stress, focusing on how these changes affect the threshold voltages and drain leakage currents of device. Using a self-built short-circuit experimental circuits for SiC MOSFETs, this article defines the most suitable repeated short-circuit electrical stresses for study of the evolution of gate-oxide interface traps. We refined the trap characterization method by optimizing the transient drain current analysis, getting the impact of traps more accurately. A differential amplitude spectrum (DAS), derived from the time constant spectrum (TCS), was employed to better describe trap effects. The study identified two critical traps: Dp<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> located near the gate oxide in the channel and Dp<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> located near the gate oxide in the junction-FET (JFET) region. The degradation of electrical properties, such as threshold voltage and drain leakage current, was linked to the evolution of these traps. Ultimately, the failure of planar SiC MOSFETs was attributed to oxide cracking between gate and source metals due to repeated short-circuit stress. This study offers valuable insights into improving the short-circuit reliability of these devices.