CARDIOEDGE: Hardware Design of Domain Specific LSTM Model for Continuous Cardiac Monitoring Devices

Cardiovascular diseases (CVDs) remain the leading cause of death worldwide with cardiacarrhythmias accounting for hundreds of thousands of deaths each year. Early and continuousmonitoring with ECG as a standard practice is essential; however, conventional systems arebulky, not energy-efficient, or operate in off-line processing, hence not available for real-timeapplications. In response, this paper presents CARDIOEDGE: a lightweight ECG-basedarrhythmia classifier using wavelet-transformed data and RR-intervals fusing time domain andfrequency domain features via a custom LSTM-based deep learning model to improveclassification fidelity. We trained the domain-specific LSTM on the MIT-BIH ArrhythmiaDatabase and then converted the trained model into C++ to use it for hardware purposes.Through Xilinx Vitis High-Level Synthesis (HLS), we synthesized the model into hardwareon a Zynq-7000 SoC (ZC702) FPGA. The design supports fixed-point arithmetic andhardware modularization, optimizing for low power and real-time performance.We synthesized the model into hardware on a Zynq-7000 SoC (ZC702) FPGA in fixed-pointarithmetic and hardware modularization, tuning for low power and real-time performance.This design supports data path widths of up to 64 bits. The output system is very high inscalability and energy efficiency, therefore ideal for use in any type of medical device, be itwearable or portable (for example smartwatches, Holter monitors, chest patches) that wouldrequire continuous on-device ECG monitoring. Further work will involve the integration of alive ECG sensor for full end-to-end real-time operation, extending the model to multi-leadECG inputs, and exploring further model compression (quantization/pruning) for even lowerpower consumption.